1. Field of the Invention
The present invention relates to a semiconductor device capable of reducing power consumption, and more particularly to a semiconductor memory device capable of reducing leakage currents at the time of a deep power down mode.
2. Description of the Prior Art
As generally known in the art, FIG. 1 is an internal circuit block diagram of a typical memory device of the prior art for explaining power consumption at the time of self-refresh mode.
In FIG. 1, one internal circuit 100 includes, for example, a circuit such as a data input/output section of the memory device consuming certain amount of electrical power even at the time of refresh mode. Another internal circuit 101 includes, for example, circuits such as a row path circuit and an internal address counter of the memory device, which become active at the time of the refresh mode. Specifically, the internal circuit 100 refers to a circuit which is not related with the self-refresh operation, whereas the internal circuit 101 refers to a circuit which is related with the self-refresh operation. In FIG. 1, an SRF (Self-Refresh Flag) signal becomes high level at the time of the self-refresh mode.
Referring to FIG. 1, when the self-refresh mode is on, the internal circuit 100 uses external power source voltage VDD as a power source, and the internal circuit 101 uses, as a power source, internal voltage VCORE of which level is lower than that of the external power source voltage VDD.
As mentioned above, when the operation of the conventional memory device is in the self-refresh mode, consumption currents IDD6 of the device can be reduced in the manner that the internal circuit uses as a power source, the internal voltage VCORE of which level is lower than that of the external power source voltage VDD.
However, in a deep power down mode (DPDM) where most of circuits of the memory device come into a disabled state except for only a minority part of all the circuits (for example, in the DPDM, the self-refresh flag signal SRF is at low level), the conventional memory devices have a problem in that electrical power energy of the external power source voltage VDD is consumed in vain, although it is not necessary to supply any power to the internal circuit 101.